1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus and a driving method using the same.
2. Related Art
In general, a semiconductor memory apparatus includes a plurality of memory cells to store data, each of which comprises a NMOS transistor and a capacitor.
FIG. 1 is a diagram showing a configuration of the memory cell of the conventional semiconductor memory apparatus. As shown in FIG. 1, the conventional memory cell includes a transistor N1 and a capacitor C1. The transistor N1 has a gate coupled to a wordline WL, a drain and a source coupled to a bitline BL and the capacitor respectively. One terminal of the capacitor C1 is coupled to the transistor N1 and the other terminal thereof is applied with a cell plate voltage VCP.
Where a data value of a logic high level is stored in the memory cell, the bitline BL receives a voltage from the capacitor C1 to increase a voltage level of the bitline BL when the wordline WL is enabled. On the contrary, where a data value of a logic low level is stored in the memory cell, the bitline BL applies a voltage to the capacitor C1 to decrease the voltage level of the bitline BL when the wordline WL is enabled.
A sense amplifier (not shown) detects the voltage level variation of the bitline BL to amplify the voltage level of the bitline BL. For example, the sense amplifier decreases the voltage level of the bitline BL to a ground voltage level when the voltage level of the bitline BL is decreased, and increases the voltage level of the bitline BL to a core voltage level when the voltage level of the bitline BL is increased. To allow the sense amplifier to operate normally as described above, it may require that a voltage level variation width of the bitline BL be equal to or greater than a predetermined voltage level width when the wordline is enabled.
In general, the semiconductor memory apparatus includes a large number of memory cells. Here if the memory cell having a data value different from that of an adjacent memory cell transfers data to the bitline (e.g., where the voltage level of the bitline is decreased, and a voltage level of an adjacent bitline is increased), the voltage level of the bitline cannot be decreased by as much as the predetermined voltage level width due to a coupling phenomenon. On the contrary, if the voltage level of the bitline is increased, and the voltage level of the adjacent bitline is decreased, the voltage level of the bitline cannot be increased by as much as the predetermined voltage level width due to the coupling phenomenon. Unless the voltage level variation width of the bitline is equal to or greater than the predetermined voltage level width, it may be difficult for the sense amplifier to perform the amplifying operation normally.